An MVA (Multi-domain Vertical Alignment) liquid crystal display device which includes vertical alignment liquid crystal is used for securing a good contrast and a wide viewing angle characteristic. This type of liquid crystal display device includes a liquid crystal layer divided into a plurality of domains which differ from each other in a direction in which the liquid crystal molecules tilt when a voltage is applied across the liquid crystal layer. This type of liquid crystal display device, however, has the following problem: Because (i) each domain has two dark lines occurring along both side edges of a projection pattern which controls an alignment direction of the liquid crystal molecules and (ii) a retardation is reduced in a portion of the liquid crystal layer which portion corresponds to a high portion of the projection pattern, a transmittance of the liquid crystal panel is reduced and accordingly a contrast ratio becomes lower. In addition, this type of liquid crystal display device has such a problem that a response speed of the liquid crystal molecules cannot be increased because a controlled alignment of the liquid crystal molecules is propagated with a delay to a portion which is not in the vicinity of the projection pattern.
In order to solve these problems, there has been proposed a liquid crystal display device provided with pixels having the configuration shown in FIG. 5. The similar configuration is disclosed in, for example, Patent Literatures 1 through 4.
FIG. 5 illustrates a configuration of a pixel PIXij which is provided so as to correspond to a portion where an numbered gate bus line GLi and a j-numbered source bus line SLj intersect with each other, the configuration being viewed in the substrate facing one side of the liquid crystal layer. The pixel PIXij is provided in a region surrounded by (i) auxiliary capacitor bus lines CSLi and CSLi+1 which are adjacent to each other and (ii) source bus lines SLj and SLj+1 which are adjacent to each other. The auxiliary capacitor bus line CSLi is provided in parallel with the gate bus line GLi, and the gate bus line GLi is provided between the auxiliary capacitor bus line CSLi and the auxiliary capacitor bus line CSLi+1.
A TFT section 111 is provided at the portion where the gate bus line GLi and the source bus line SLj intersect with each other. The TFT section 111 includes two gate electrodes, i.e., gate electrodes 111g(1) and 111g(2). The gate electrode 111g(1) is an electrode drawn from the gate bus line GLi, and intersects with the source bus line SLj so as to be closer to the auxiliary capacitor bus line CSLi+1 than the gate bus line GLi is. The gate electrode 111g(2) is a part of the gate bus line GLi which part includes the portion where the gate bus line GLi intersects with the source bus line SLj.
There formed a Si conductive layer right below the source bus line SLj, which Si conductive layer is disposed above the gate electrodes 111g(1) and 111g(2) so as to intersect with the gate electrodes 111g(1) and 111g(2). A portion of the Si conductive layer which portion is closer to the auxiliary capacitor bus line CSLi+1 than the gate electrode 111g(1) is constitutes a source section 111s of the TFT section 111, and a portion of the Si conductive layer which portion is closer to the auxiliary capacitor bus line CSLi than the gate electrode 111g(2) is constitutes a drain section 111d of the TFT section 111. The source section 111s is connected with the source bus line SLj through a contact hole 111h. The drain section 111d is routed to the inside of the pixel region, and is connected with a connecting wire 115 through a contact hole 121h, which connecting wire 115 is disposed above the drain section 111d. The connecting wire 115 is connected with a pixel electrode 105 through a contact hole 125h, which pixel electrode 105 is disposed above the connecting wire 115. Further, the drain section 111d is routed from the inside of the pixel region to a position above the auxiliary capacitor bus line CSLi, and is connected with an auxiliary capacitor electrode pad CSP which is disposed to be opposed to the auxiliary capacitor bus line CSLi from above the auxiliary capacitor bus line CSLi. The auxiliary capacitor bus line CSLi and the auxiliary capacitor electrode pad CSP form an auxiliary capacitance Cs.
The pixel electrode 105 is made of a transparent electrode, and includes a main line 105a, a main line 105b, and stripe portions 105c. The main line 105a is provided to extend in parallel with the source bus line SLj, and the main line 105b is provided to extend in parallel to the gate bus line GLi. The main line 105a and the main line 105b are cross-connected with each other at a center of the pixel PIXij, on a surface of the panel. Disposing the main line 105a and the main line 105b as described above provides, in the pixel electrode 105, four regions R1, R2, R3, and R4 divided by the main line 105a and the main line 105b. Each of the regions includes a plurality of stripe portions 105c extending in the same direction which forms an angle of 45 degrees with respect to the gate bus line GLi and the source bus line SLj. The plurality of stripe portions 105c are connected with the main lines 105a and 105b. Each of the regions includes a cut-out pattern 106 between a stripe portion 105c and its adjacent stripe portion 105c, in which cut-out pattern 106 no transparent electrode is formed. This provides a striped electrode pattern in which the stripe portions 105 are periodically arranged in a direction orthogonal to the direction in which the stripe portions 105c extend. A stripe line direction (in which the stripe portions 105c extend) of a region differs by 90 degrees from that of its adjacent region neighboring across the main line 105a or the main line 105b. In a case where the pixel electrode 105 region extends beyond the stripe portions 105c and reaches an outer peripheral of the pixel PIXij, the stripe portions 105c are also connected with an outer peripheral region of the pixel electrode 105.
The contact between the connecting wire 115 and the pixel electrode 105 through the contact hole 125h is made in the vicinity of a portion right below the main line 105a. 
A substrate having the above-described configuration and a counter substrate opposed to this substrate sandwich a vertical alignment liquid crystal layer. Applying a voltage to the pixel electrode 105 and an electrode of the counter substrate causes the liquid crystal layer to be driven. Further, the configuration in which the liquid crystal layer is sandwiched by these two substrates is externally sandwiched by two polarization plates, each of which polarization plates is made of a linear polarization plate. One of the polarization plates is set so that its light absorption axis is in parallel with the main line 105a, and the other one of the polarization plates is set so that its light absorption axis is in parallel with the main line 105b. 
According to the above-described pixel PIXij, as shown in (a) of FIG. 6, while liquid crystal molecules MLC are driven, the liquid crystal molecules MLC tilt along a direction in which the cut-out pattern 106 extends, due to an effect of an electric field which is formed by the cut-out pattern 106 and which changes periodically in a direction orthogonal to the direction in which the cut-out pattern 106 extends. A side of each liquid crystal molecule MLC which side is depicted as wider in (a) of FIG. 6 points to the counter substrate during a vertical alignment mode. This side of each liquid crystal molecule tilts toward the main line 105a (or 105b). On the main line 105a (or 105b), the liquid crystal molecules tilt in an up-to-down direction in FIG. 6 from its vertical orientation state.
Since the light absorption axes of the two linear polarization plates are set to form a cross defined by (i) the direction parallel with the main line 105a and (ii) the direction orthogonal to the direction parallel with the main line 105a, a dark line occurs on each of the main lines 105a and 105b. However, unlike in conventional ones, two dark lines do not occur along both side edges of one projection pattern. Therefore, a transmittance during a driving mode is significantly improved. In addition, since the direction in which the liquid crystal molecules MC tilt is not defined by tilting of other liquid crystal molecules MLC, the liquid crystal molecules can be quickly changed from a vertical orientation state to a horizontal orientation state, and vice versa, that is, a response speed is very high. Furthermore, since the regions R1 to R4 are different from each other in the direction in which the liquid crystal molecules MLC tilt, the liquid crystal display device can exhibit a wide viewing angle characteristic.
Patent Literature 1: Japanese Patent Application Publication, Tokukai, No. 2002-107730 A (Publication Date: Apr. 10, 2002)
Patent Literature 2: Japanese Patent Application Publication, Tokukai, No. 2003-149647 A (Publication Date: May 21, 2003)
Patent Literature 3: Japanese Patent Application Publication, Tokukai, No. 2003-177418 A (Publication Date: Jun. 27, 2003)
Patent Literature 4: Japanese Patent Application Publication, Tokukai, No. 2003-255305 A (Publication Date: Sep. 10, 2003)
Patent Literature 5: Japanese Patent Application Publication, Tokukai, No. 2006-208881 A (Publication Date: Aug. 10, 2006)
Patent Literature 6: Japanese Patent Application Publication, Tokukai, No. 2002-289857 A (Publication Date: Oct. 4, 2002)